Field of the Invention:
The present invention relates generally to semiconductor, and more particularly to a semiconductor device including a polycrystalline silicon diode.
Polycrystalline silicon has been widely used in semiconductor circuits and devices as passive elements such as gate electrodes, wirings, and resistors. Moreover, the art of forming a diode, that is, a P-N junction, in polycrystalline silicon has been practiced in fields such as the field of solar batteries. In such a diode formed in polycrystalline silicon, a recombination-generation current is predominant, and it is, therefore, expected that the forward voltage in this diode will be smaller than that in a diode formed in monocrystalline silicon. In addition, since the lifetime of minority carriers in a polycrystal is very short due to the large number of recombination centers caused by grain boundaries, fast operation of a polycrystalline diode appears to be attainable.
However, in the formation of a P-N junction in polycrystalline silicon in the prior art, a major surface of a monocrystalline semiconductor substrate is covered with an insulator film on which polycrystalline silicon layer of one conductivity type is formed, and an impurity region of the opposite conductivity type is formed in the polycrystalline silicon layer from its surface to a certain depth. In such a structure, it is difficult to stably form a P-N junction in a polycrystalline silicon layer due to the fact that fluctuations of the thickness of the polycrystalline silicon layer, as well as the diffusion constant of an impurity in polycrystalline silicon, are large. It has also been proposed to form the region of the opposite conductivity type so deep that it may reach the insulator film. However, according to this method, the junction area of the P-N junction is reduced because the junction is formed only along a side surface of the region of the opposite conductivity type, resulting in an increase of current density, so that the forward voltage becomes high. These prior art techniques are disclosed, for example, in Solid-State Electronics, 1972 Vol. 15, p.p. 1103-1106.
The power-speed product is recognized as one of the indexes representing the performance of a logic circuit. This index is proportional to the product of three parameters, circuit voltage, logic amplitude voltage, and circuit capacity. For optimum logic circuit performance it is desirable that this product be made as low as possible. One approach for improving the power speed product has been to reduce the a logic amplitude by making use of a Schottky barrier diode. As one example, a Schottky I.sup.2 L (Integrated Injection Logic) has been developed. However, it is difficult to combine an I.sup.2 L and a Schottky diode, because the collector of a transistor in the I.sup.2 L would have a high impurity concentration due to the structural requirement for an integrated circuit, and it is difficult to form a Schottky barrier on the collector region. To this end, an attempt has been made to form the base by the injection of high energy ions, thereby to lower the surface impurity concentration of the collector region. However, it is difficult in this approach to achieve a cut off frequency f.sub.T of an NPN transistor of a sufficiently high value, such that the advantage obtained by employing a Schottky barrier diode would be lost. Such an I.sup.2 L is disclosed, for example, at IEEE J. of Solid State Circuits, Vol. SC-10, No. 5, Oct. 1975, p.p. 343-348.